The present invention generally relates to an improved digital multiplication system. The present invention more particularly relates to such a system for efficiently performing a series of multiplications of plural pairs of first and second operands to derive a series of multiplication products. The present invention is still further directed to such a system capable of accumulating the multiplication products and which performs the multiplications and accumulations in fewer operating cycles than heretofore possible.
Digital multiplication and accumulation are often required of digital signal processors for many applications. One such application is in the implementation of Recommendation G.721 for use in cordless portable telephony. One function required in Recommendation G.721 is the performance of eight serial multiplications of eight different pairs of first and second multiple-bit binary operands and the accumulation of the multiplication products. In addition, Recommendation G.721 requires, to perform this function, one set of operands to be in floating point format, the second set of operands to be in fixed point format, and the accumulated product to be in fixed point format.
Digital signal processors generally are in integrated circuit form for such an application and are powered by portable power sources such as a battery. It is therefore advantageous for such digital signal processors to perform their required functions in a minimum number of operating cycles to conserve battery power. Unfortunately, prior art digital signal processors generally require a great number of operating cycles to perform this serial multiplication and accumulation required by Recommendation G.721. For example, one digital signal processor required 396 operating cycles, another digital signal processor required 354 cycles, and still another digital signal processor requires 122 operating cycles to perform this G.721 function. Obviously, any reduction in the number of operating cycles to perform this G.721 function would represent an advantage in conserving battery power.
The multiplication system of the present invention may be utilized to advantage in a digital signal processor for performing the aforementioned multiplication and accumulation function required by Recommendation G.721. It requires just 31 operating cycles to complete the required function representing a considerable savings in execution time and battery power. In addition, the multiplication system of the present invention is structured in a pipelined arrangement to not only reduce the required operating cycles, but in addition, the sections of the multiplication and accumulation system not currently active may be powered down to further conserve power. Further, all of the operands may be stored in a single memory.